1. Field of the Invention
The present invention relates generally to semiconductor devices and methods of manufacturing thereof, and more specifically, to a structure of a DRAM (Dynamic Random Access Memory) and a method of manufacturing thereof.
2. Description of the Background Art
Conventionally, demands for semiconductor memory devices have expanded rapidly with information equipments coming into wide use. Furthermore, there exists a demand for a device having a large storage capacity and capable of high speed operation. Accordingly, recent development is under way on semiconductor devices in relation to high density integration, high speed response, and high reliability.
Among various semiconductor memory devices, a DRAM is known as allowing random input and output of storage information. A DRAM generally includes a memory cell array portion which is a storage region in which a plurality of pieces of information are stored, and peripheral circuitry necessary for external input and output. FIG. 68 is a block diagram showing a general structure of a DRAM. Referring to FIG. 68, a DRAM 150 includes a memory cell array 151 for storing a data signal of storage information, a row and column address buffer 152 for receiving an external address signal to select a memory cell constituting a unit storage circuit, a row decoder 153 and a column decoder 154 for designating the memory cell by decoding the address signal, a sense refresh amplifier 155 for amplifying a signal stored in the designated memory cell and reading out the signal, a data in buffer 156 and a data out buffer 157 for inputting and outputting data, and a clock generator 158 for generating a clock signal.
Memory cell array 151 which occupies a large area on a semiconductor chip has a plurality of memory cells in a matrix for storing unit storage information. More specifically, a memory cell is usually formed of an MOS transistor and a capacitor connected thereto. The memory cell is widely known as a memory cell of 1 transistor per 1 capacitor type. A memory cell of such a structure is advantageous for increasing the integration density of a memory cell array for its simple structure, and, therefore, widely used for a DRAM of a large capacity.
Memory cells for DRAMs can be divided into several types due to the structures of their capacitors. Among them, a stacked type capacitor can increase the capacity of a capacitor by increasing the facing area between the electrodes of capacitors by extending the essential part of the capacitor over a gate electrode or a field oxide film. The stacked type capacitor with such a feature, can secure the capacity of the capacitor even when devices are reduced in size due to an increasing integration density of a semiconductor device. As a result, with high density integration of semiconductor devices, more stacked type capacitors have been used. These capacitors are for example disclosed in U.S. Pat. No. 4,907,046.
FIG. 69 is a cross sectional view of a structure of a DRAM including a conventional stacked type capacitor. Referring to FIG. 69, the conventional DRAM includes a P type silicon substrate 201, a field oxide film 202 for isolating elements formed in a prescribed region on the main surface of P type silicon substrate 201, source/drain regions 203a and 203b formed a prescribed distance apart from each other with a channel region 214 therebetween in an active region surrounded by field oxide film 202, a gate electrode 205 formed on a channel region 214 with a gate oxide film 204 therebetween, an interlayer insulating film 206 formed covering gate electrode 205, a capacitor lower electrode 207 electrically connected to source/drain region 203a and formed extending on the upper part of gate electrode 205 with interlayer insulating film 206 therebetween, a capacitor insulating film 208 formed covering capacitor lower electrode 207, a capacitor upper electrode 209 formed covering capacitor insulating film 208, an interlayer insulating film 210 having a contact hole 210a on source/drain region 203b, a bit line 211 electrically connected to source/drain region 203b in contact hole 210a and extending along the surface of interlayer insulating film 210, an interlayer insulating film 212 formed covering bit line 211 and having its surface planarized, and an aluminum interconnection 213 formed on interlayer insulating film 212 and corresponding to gate electrode 205. Capacitor lower electrode 207 and capacitor upper electrode 209 are formed of polysilicon. Bit line 211 is formed of an aluminum film. Capacitor insulating film 208 is formed of a silicon oxide film.
A pair of source/drain regions 203a and 203b, and gate electrode 205 constitute the transfer gate transistor of a memory cell. Capacitor lower electrode 207, capacitor insulating film 208, and capacitor upper electrode 209 constitute a stacked type capacitor for storing charge corresponding to a data signal.
In a writing operation, charge corresponding to a data signal is transferred to source/drain region 203b through bit line 211. Applying a prescribed voltage to gate electrode 205 turns on the transfer gate transistor. Thus, the charge transferred to source/drain region 203b is further transferred to capacitor lower electrode 207 through channel region 214 and source/drain region 203a. As a result, the charge corresponding to the data signal is stored in the capacitor.
In a reading operation, applying a prescribed voltage to gate electrode 205 turns on the transfer gate transistor. Thus, charge stored in the capacitor is transferred to source/drain region 203b through source/drain region 203a and channel region 214. The charge transferred to source/drain region 203b is read out externally through bit line 211.
FIGS. 70-78 are cross-sectional views for use in illustration of a manufacturing process (from a first step to a ninth step) of the conventional DRAM shown in Fig. 69. Referring to FIGS. 69 and 70-78, a description of a manufacturing process of the conventional DRAM follows.
Now, as shown in FIG. 70, field oxide film 202 for element isolation is formed in a prescribed region on the main surface of P type silicon substrate 201 by means of thermal oxidation. A gate oxide film layer (not shown) is formed by means of thermal oxidation, and a polysilicon layer (not shown) is formed on the gate oxide film layer by chemical vapor deposition. Gate oxide film 204 and gate electrode 205 are formed by means of photolithography and etching techniques. Source/drain regions 203a and 203b are formed by implanting ions using gate electrode 205 as mask. Interlayer insulating film 206 covering gate electrode 205 is formed by means of chemical vapor deposition or the like.
As shown in FIG. 71, a polysilicon layer 207a is formed by means of CVD on the entire surface.
Then, as shown in FIG. 72, using photolithography and etching techniques, polysilicon layer 207a (see FIG. 71) is patterned to form capacitor lower electrode 207.
Then, as shown in FIG. 73, silicon oxide film (capacitor insulating film) 208 is formed on the surface of capacitor lower electrode 207 by means of thermal oxidation.
Then, as shown in FIG. 74, polysilicon layer 209a is formed by chemical vapor deposition. Using photolithography and etching techniques, polysilicon layer 209a is patterned to form capacitor upper electrode 209 as shown in FIG. 75.
As shown in FIG. 76, interlayer insulating film 210 is formed by chemical vapor deposition. Then, as shown in FIG. 77, using the photolithography and etching techniques, contact hole 210a is formed in interlayer insulating film 210. Thus, the surface of source/drain region 203b is exposed.
As shown in FIG. 78, an aluminum film to be a bit line is formed to be electrically connected to source/drain region 203b by sputtering.
Finally, as shown in FIG. 69, interlayer insulating film 212 is formed on bit line 211. The surface of interlayer insulating film 212 is a planarized by reflow process. Then, aluminum interconnection 213 is formed on interlayer insulating film 212 corresponding to gate electrode 205. Thus, the DRAM having the conventional stacked type capacitor is completed.
As described above, conventionally, in order to secure a certain capacity of a capacitor even when elements are reduced in size due to an increased integration of semiconductor device, stacked type capacitors having a structure shown in FIG. 69 are used.
The structure of FIG. 69 however makes it difficult to secure a certain capacity of a capacitor with further down scaling of elements. More specifically, when the elements are further reduced in size, in the structure shown in FIG. 69, the facing area between capacitor lower electrode 207 and capacitor upper electrode 209 decreases. It is therefore difficult to secure a sufficient capacity of a capacitor for maintaining stable storage of data as the capacity of the capacitor is reduced and the elements are further reduced in size.